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High Speed, Triple Differential Receiver with Comparators AD8143
FEATURES
High speed 160 MHz large signal bandwidth 1000 V/s slew rate @ G = 1, VO = 2 V p-p High CMRR: 65 dB @ 10 MHz High differential input impedance: 5 M Input common-mode range: 10.5 V (12 V supplies) User-adjustable gain Wide power supply range: +5 V to 12 V Fast settling: 8 ns to 1% Disable feature Low offset: 3.4 mV on 5 V supply 2 on-chip comparators Small packaging: 32-lead, 5 mm x 5 mm LFCSP
GND
PIN CONFIGURATION
DIS/PD REF_B IN+_B IN-_B FB_B GND
25
32
31
30
29
28
27
26
VS-
GND REF_G FB_G IN+_G IN-_G REF_R FB_R GND
1
24
GND OUT_B OUT_G OUT_R VS+ COMPB_IN+ COMPB_IN- GND
2
23
3
22
4
21
5
AD8143
20
6 B 7 A
19
18
APPLICATIONS
RGB video receivers KVM (keyboard-video-mouse) UTP (unshielded twisted pair) receivers
8
17
9
10
11
12
13
14
15
16
COMPA_IN+
COMPA_OUT
COMPB_OUT
COMPA_IN-
IN+_R
IN-_R
GND
GND
Figure 1.
GENERAL DESCRIPTION
The AD8143 is a triple, low cost, differential-tosingle-ended receiver specifically designed for receiving red-green-blue (RGB) signals over twisted pair cable. It can also be used for receiving any type of analog signal or high speed data transmission. Two auxiliary comparators are provided to receive digital or sync signals. The AD8143 can be used in conjunction with the AD8133 and AD8134 triple, differential drivers to provide a complete low cost solution for RGB over Category-5 UTP cable applications, including KVM. The excellent common-mode rejection (65 dB @ 10 MHz) of the AD8143 allows for the use of low cost unshielded twisted pair cables in noisy environments. The AD8143 has a wide power supply range from single +5 V supply to 12 V, which allows for a wide common-mode range. The wide common-mode input range of the AD8143 maintains signal integrity in systems where the ground potential is a few volts different between the drive and receive ends without the use of isolation transformers. The AD8143 is stable at a gain of 1. Closed-loop gain is easily set using external resistors. The AD8143 is available in a 5 mm x 5 mm, 32-lead LFCSP and is rated to work over the extended industrial temperature range of -40C to +85C.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c) 2005 Analog Devices, Inc. All rights reserved.
05538-001
AD8143 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Pin Configuration............................................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 9 Thermal Resistance ...................................................................... 9 ESD Caution.................................................................................. 9 Pin Configuration and Function Descriptions........................... 10 Typical Performance Characteristics ........................................... 11 Theory of Operation ...................................................................... 17 Applications..................................................................................... 18 Overview ..................................................................................... 18 Basic Closed-Loop Gain Configurations ................................ 18 Terminating the Input................................................................ 19 Input Clamping........................................................................... 19 Printed Circuit Board Layout Considerations ....................... 20 Driving a Capacitive Load......................................................... 22 Power-Down ............................................................................... 22 Comparators ............................................................................... 22 Sync Pulse Extraction Using Comparators ............................. 22 Outline Dimensions ....................................................................... 24 Ordering Guide .......................................................................... 24
REVISION HISTORY
10/05--Revision 0: Initial Version
Rev. 0 | Page 2 of 24
AD8143 SPECIFICATIONS
VS = 12 V, TA = 25C, REF = 0 V, RL = 150 , CL = 2 pF, G = 1, TMIN to TMAX = -40C to +85C, unless otherwise noted. Table 1.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1dB Flatness Slew Rate Settling Time Output Overdrive Recovery NOISE/DISTORTION Second Harmonic Third Harmonic Crosstalk Input Voltage Noise (RTI) Differential Gain Error Differential Phase Error INPUT CHARACTERISTICS Common-Mode Rejection Conditions VOUT = 0.2 V p-p VOUT = 2 V p-p VOUT = 0.2 V p-p VOUT = 2 V p-p, RL = 1 k VOUT = 2 V p-p, 1% VOUT = 2 V p-p, 0.1% Min Typ 260 160 45 1000 8 31 50 -70 -80 -70 14 0.03 0.06 86 90 65 28 10.5 2.5 5 3 2 3 70 0.25 -4.3 TMIN to TMAX Input Bias Current (+IN, -IN) Input Bias Current (REF, FB) Input Bias Current Drift Input Offset Current Input Offset Current Drift OUTPUT PERFORMANCE Voltage Swing Output Current Short Circuit Current COMPARATOR PERFORMANCE VOH VOL Hysteresis Width Input Bias Current Propagation Delay, tPLH Propagation Delay, tPHL Output Rise Time Output Fall Time -3.0 -4.6 TMIN to TMAX (+IN, -IN) (+IN, -IN, REF, FB) TMIN to TMAX RLOAD = 1 k Short to GND, source/sink 3.135 16 -2.55 3 -10.80 40 107/147 3.3 0.2 41 3.5 20 15 15 11 +10.82 +1.45 15 +3.0 +3.7 +4.3 Max Unit MHz MHz MHz V/s ns ns ns dBc dBc dB nV/Hz % Degrees dB dB dB V V M M pF pF dB % mV V/C A A nA/C A nA/C V mA mA V V mV A ns ns ns ns
VOUT = 2 V p-p, 1 MHz VOUT = 2 V p-p, 1 MHz VOUT = 1 V p-p, 10 MHz f 10 kHz NTSC, 200 IRE, RL 150 NTSC, 200 IRE, RL 150 DC, VCM = -3.5 V to +3.5 V VCM = 1 V p-p, f = 10 MHz VCM = 1 V p-p, f = 100 MHz V+IN - V-IN = 0 V Differential Common-mode Differential Common-mode VOUT = 1 V DC
Common-Mode Voltage Range Differential Operating Range Resistance Capacitance DC PERFORMANCE Open-Loop Gain Closed-Loop Gain Error Input Offset Voltage
0.255
Input driven low RL = 10 k RL = 10 k 25% to 75%, RL = 10 k 25% to 75%, RL = 10 k
Rev. 0 | Page 3 of 24
AD8143
Parameter POWER-DOWN PERFORMANCE Power-Down VIH Power-Down VIL Power-Down IIH Power-Down IIL Power-Down Assert Time POWER SUPPLY Operating Range Quiescent Current, Positive Supply Quiescent Current, Negative Supply PSRR, Positive Supply PSRR, Negative Supply Conditions Min Typ VS+ - 1.5 VS+ - 2.5 1.0 800 0.5 4.5 44.0 37.0 -75 -82 24 57.5 51.0 -71 -81 Max Unit V V A A s V mA mA dB dB
PD = VCC PD = GND
DC DC
Rev. 0 | Page 4 of 24
AD8143
VS = 5 V, TA = 25C, REF = 0 V, RL = 150 , CL = 2 pF, G = 1, TMIN to TMAX = -40C to +85C, unless otherwise noted. Table 2.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1dB Flatness Slew Rate Settling Time Output Overdrive Recovery NOISE/DISTORTION Second Harmonic Third Harmonic Crosstalk Input Voltage Noise (RTI) Differential Gain Error Differential Phase Error INPUT CHARACTERISTICS Common-Mode Rejection Conditions VOUT = 0.2 V p-p VOUT = 2 V p-p VOUT = 0.2 V p-p VOUT = 2 V p-p, RL = 1 k VOUT = 2 V p-p, 1% VOUT = 2 V p-p, 0.1% Min Typ 230 130 45 1000 10 23 50 -68 -82 -70 14 0.3 0.6 84 90 65 28 3.8 2.5 5 3 2 3 70 0.25 -3.7 TMIN to TMAX Input Bias Current (+IN, -IN) Input Bias Current (REF, FB) Input Bias Current Drift Input Offset Current Input Offset Current Drift OUTPUT PERFORMANCE Voltage Swing Output Current Short Circuit Current COMPARATOR PERFORMANCE VOH VOL Hysteresis Width Input Bias Current Propagation Delay, tPLH Propagation Delay, tPHL Output Rise Time Output Fall Time -3.0 -4.3 TMIN to TMAX (+IN, -IN, REF, FB) (+IN, -IN, REF, FB) TMIN to TMAX RLOAD = 150 Short to GND, source/sink RL = 10 k RL = 10 k Input driven low 3.02 16 -2.9 3 -3.53 40 107/147 3.14 0.19 32 3.5 20 15 15 11 +3.53 1.9 15 +2.7 +3.0 +3.7 Max Unit MHz MHz MHz V/s ns ns ns dBc dBc dB nV/Hz % Degrees dB dB dB V V M M pF pF dB % mV V/C A A nA/C A nA/C V mA mA V V mV A ns ns ns ns
VOUT = 1 V p-p, 1 MHz VOUT = 1 V p-p, 1 MHz VOUT = 1 V p-p, 10 MHz f 10 kHz NTSC, 200 IRE, RL 150 NTSC, 200 IRE, RL 150 DC, VCM = -3.5 V to +3.5 V VCM = 1 V p-p, f = 10 MHz VCM = 1 V p-p, f = 100 MHz V+IN - V-IN = 0 V Differential Common-mode Differential Common-mode VOUT = 1 V DC
Common-Mode Voltage Range Differential Operating Range Resistance Capacitance DC PERFORMANCE Open-Loop Gain Closed-Loop Gain Error Input Offset Voltage
0.25
10% to 90% 10% to 90%
Rev. 0 | Page 5 of 24
AD8143
Parameter POWER-DOWN PERFORMANCE Power-Down VIH Power-Down VIL Power-Down IIH Power-Down IIL Power-Down Assert Time POWER SUPPLY Operating Range Quiescent Current, Positive Supply Quiescent Current, Negative Supply PSRR, Positive Supply PSRR, Negative Supply Conditions Min Typ VS+ - 1.5 VS+ - 2.5 1 230 0.5 4.5 39.0 34.5 -80 -80 24 49.5 43.5 -74 -75 Max Unit V V A A s V mA mA dB dB
PD = VCC PD = GND
DC DC
Rev. 0 | Page 6 of 24
AD8143
VS = 5 V, TA = 25C, REF = +2.5 V, RL = 150 , CL = 2 pF, G = 1, TMIN to TMAX = -40C to +85C, unless otherwise noted. Table 3.
Parameter DYNAMIC PERFORMANCE -3 dB Bandwidth Bandwidth for 0.1dB Flatness Slew Rate Settling Time Output Overdrive Recovery NOISE Crosstalk Input Voltage Noise (RTI) INPUT CHARACTERISTICS Common-Mode Rejection Conditions VOUT = 0.2 V p-p VOUT = 2 V p-p VOUT = 0.2 V p-p VOUT = 2 V p-p, RL = 1 k VOUT = 2 V p-p, 1% VOUT = 2 V p-p, 0.1% Min Typ 220 125 45 1000 10 23 50 -70 14 76 90 65 32 1.3 to 3.7 2.5 5 3 2 3 70 0.25 -3.4 TMIN to TMAX Input Bias Current (+IN, -IN) Input Bias Current (REF, FB) Input Bias Current Drift Input Offset Current Input Offset Current Drift OUTPUT PERFORMANCE Voltage Swing Output Current Short Circuit Current COMPARATOR PERFORMANCE VOH VOL Hysteresis Width Input Bias Current Propagation Delay, tPLH Propagation Delay, tPHL Output Rise Time Output Fall Time POWER-DOWN PERFORMANCE Power-Down VIH Power-Down VIL Power-Down IIH Power-Down IIL Power-Down Assert Time -3 -4.5 TMIN to TMAX (+IN, -IN, REF, FB) (+IN, -IN, REF, FB) TMIN to TMAX RLOAD = 150 Short to GND RL = 10 k RL = 10 k Input driven low 3.02 0.25 32 3.5 20 15 15 11 VS+ - 1.5 VS+ - 2.5 1 230 0.5 16 -2.3 3 0.88 40 150 3.58 +1.3 15 +2.7 +3 +3.4 Max Unit MHz MHz MHz V/s ns ns ns dB nV/Hz dB dB dB V V M M pF pF dB % mV V/C A A nA/C A nA/C V mA mA V V mV A ns ns ns ns V V A A s
VOUT = 1 V p-p, 10 MHz f 10 kHz DC, VCM = -3.5 V to +3.5 V VCM = 1 V p-p, f = 10 MHz VCM = 1 V p-p, f = 100 MHz V+IN - V-IN = 0 V Differential Common-mode Differential Common-mode VOUT = 1 V DC, measured at G = 11
Common-Mode Voltage Range Differential Operating Range Resistance Capacitance DC PERFORMANCE Open-Loop Gain Closed-Loop Gain Error Input Offset Voltage
10% to 90% 10% to 90%
PD = VCC PD = GND
Rev. 0 | Page 7 of 24
AD8143
Parameter POWER SUPPLY Operating Range Quiescent Current, Positive Supply PSRR, Positive Supply Conditions Min 4.5 DC 31.5 -86 Typ Max 24 38.8 -76 Unit V mA dB
Rev. 0 | Page 8 of 24
AD8143 ABSOLUTE MAXIMUM RATINGS
Table 4.
Parameter Supply Voltage Power Dissipation Storage Temperature Range Operating Temperature Range Lead Temperature Range (Soldering 10 sec) Junction Temperature Rating 24 V See Figure 2 -65C to +125C -40C to +85C 300C 150C
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
The power dissipated in the package (PD) is the sum of the quiescent power dissipation and the power dissipated in the package due to the load drive for all outputs. The quiescent power is the voltage between the supply pins (VS) times the quiescent current (IS). The power dissipated due to the load drive depends upon the particular application. For each output, the power due to load drive is calculated by multiplying the load current by the associated voltage drop across the device. The power dissipated due to all of the loads is equal to the sum of the power dissipation due to each individual load. RMS voltages and currents must be used in these calculations. Airflow increases heat dissipation, effectively reducing JA. In addition, more metal directly in contact with the package leads from metal traces, through-holes, ground, and power planes reduces the JA. The exposed paddle on the underside of the package must be soldered to a pad on the PCB surface which is thermally connected to a copper plane to achieve the specified JA. Figure 2 shows the maximum safe power dissipation in the package vs. the ambient temperature for the 32-lead LFCSP (45C/W) on a JEDEC standard 4-layer board with the underside paddle soldered to a pad which is thermally connected to a PCB plane. Extra thermal relief is required for operation at high supply voltages. See the Applications section for details. JA values are approximations.
4.5
THERMAL RESISTANCE
JA is specified for the worst-case conditions, that is, JA is specified for a device soldered in the circuit board with its exposed paddle soldered to a pad on the PCB surface which is thermally connected to a copper plane. Table 5. Thermal Resistance
Package Type 5 mm x 5 mm, 32-Lead LFCSP JA 45 JC 7 Unit C/W
Maximum Power Dissipation
MAXIMUM POWER DISSIPATION (W)
The maximum safe power dissipation in the AD8143 package is limited by the associated rise in junction temperature (TJ) on the die. At approximately 150C, which is the glass transition temperature, the plastic changes its properties. Even temporarily exceeding this temperature limit can change the stresses that the package exerts on the die, permanently shifting the parametric performance of the AD8143. Exceeding a junction temperature of 150C for an extended period can result in changes in the silicon devices potentially causing failure.
4.0 3.5 3.0 2.5 2.0 1.5
05538-056
1.0 0.5 -40
-20
0
20
40
60
80
AMBIENT TEMPERATURE (C)
Figure 2. Maximum Power Dissipation vs. Temperature for a 4-Layer Board
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although this product features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
Rev. 0 | Page 9 of 24
AD8143 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
DIS/PD REF_B IN+_B IN-_B FB_B GND
32 31 30 29 28 27 26 25
GND
VS-
GND REF_G FB_G IN+_G IN-_G REF_R FB_R GND
1
24
GND OUT_B OUT_G OUT_R VS+ COMPB_IN+ COMPB_IN- GND
2
23
3
22
4
21
AD8143
5
TOP VIEW (Not to Scale)
B
20
6
19
7
A
18
8
17
9
10
11
12
13
14
15
16
COMPA_IN+
COMPA_OUT
COMPB_OUT
COMPA_IN-
IN+_R
IN-_R
GND
GND
Figure 3. 32-Lead LFCSP Pin Configuration
Note exposed pad on underside of device must be connected to ground. Table 6. 32-Lead LFCSP Pin Function Descriptions
Pin No. 1, 8, 9,16, 17, 24, 25, 32 2 3 4 5 6 7 10 11 12 13 14 15 18 19 20 21 22 23 26 27 28 29 30 31 Exposed Underside Pad Mnemonic GND REF_G FB_G IN+_G IN-_G REF_R FB_R IN+_R IN-_R COMPA_IN+ COMPA_IN- COMPA_OUT COMPB_OUT COMPB_IN- COMPB_IN+ VS+ OUT_R OUT_G OUT_B VS- DIS/PD REF_B FB_B IN+_B IN-_B GND Description Signal Ground and Thermal Plane Connection (See the Applications Section) Reference Input, Green Channel Feedback Input, Green Channel Noninverting Input, Green Channel Inverting Input, Green Channel Reference Input, Red Channel Feedback Input, Red Channel Noninverting Input, Red Channel Inverting Input, Red Channel Positive Input, Comparator A Negative Input, Comparator A Output, Comparator A Output, Comparator B Negative Input, Comparator B Positive Input, Comparator B Positive Power Supply Output, Red Channel Output, Green Channel Output, Blue Channel Negative Power Supply Disable/Power Down Reference Input, Blue Channel Feedback Input, Blue Channel Noninverting Input, Blue Channel Inverting Input, Blue Channel Signal Ground and Thermal Plane Connection (See the Applications Section)
Rev. 0 | Page 10 of 24
05538-050
AD8143 TYPICAL PERFORMANCE CHARACTERISTICS
Unless otherwise noted, G = 1, RL = 150 , CL = 2 pF, VS = 5 V, TA = 25C. Refer to the circuit in Figure 38.
3 2 VS = 5 1 0 1 VS = 12 0 3 2
GAIN (dB)
VS = 12 -2 -3 -4 VS = +5 -5
05538-002
GAIN (dB)
-1
-1 -2 VS = 5 -3 -4 -5 -6 -7 1 10 FREQUENCY (MHz) 100
05538-005
VOUT = 0.2V p-p -6 -7 1 10 FREQUENCY (MHz) 100
VOUT = 2V p-p
VS = +5
Figure 4. Small Signal Frequency Response at Various Power Supplies, G = 1
Figure 7. Large Signal Frequency Response at Various Power Supplies, G = 1
9 8 VS = 5 7 6 VS = +5
9 VS = +5 8 7 6 VS = 12 VS = 5
GAIN (dB)
GAIN (dB)
5 4 4 2 1
05538-003
5 VS = 12 4 3 2 1 0 -1 1 10 FREQUENCY (MHz) 100
05538-006
VOUT = 0.2V p-p 0 -1 1 10 FREQUENCY (MHz) 100
VOUT = 2V p-p
Figure 5. Small Signal Frequency Response at Various Power Supplies, G = 2
3 2 RL = 1k 1 0
Figure 8. Large Signal Frequency Response at Various Power Supplies, G = 2
3 2 1 RL = 1k 0 RL = 150
GAIN (dB)
GAIN (dB)
-1 -2 -3 -4 -5
05538-004
-1 RL = 150 -2 -3 -4
-6 -7 1 10 FREQUENCY (MHz) 100
-6 -7 1 10 FREQUENCY (MHz) 100
Figure 6. Small Signal Frequency Response at Various Loads
Figure 9. Large Signal Frequency Response at Various Loads
Rev. 0 | Page 11 of 24
05538-007
VOUT = 0.2V p-p
-5 VOUT = 2V p-p
AD8143
5 4 G = 1, CL = 10pF, RSNUB = 40 3 G = 1, CL = 2pF 2 G = 2, CL = 10pF, RSNUB = 40 2 3 G = 1, CL = 10pF, RSNUB = 40 G = 2, CL = 10pF, RSNUB = 40 5 4
GAIN (dB)
0 -1 -2 -3
05538-013
GAIN (dB)
1
1 0 -1 -2 -3 -4 -5 1 10 100 FREQUENCY (MHz)
05538-014
G = 2, CL = 2pF
G = 2, CL = 2pF G = 1, CL = 2pF
-4 -5 1
RL = 1k VOUT = 0.2V p-p 10 100
RL = 1k VOUT = 2V p-p
1000
1000
FREQUENCY (MHz)
Figure 10. Small Signal Frequency Response at Various Gains and 10 pF Capacitive Load Buffered by 40 Resistor
Figure 13. Large Signal Frequency Response at Various Gains and 10 pF Capacitive Load Buffered by 40 Resistor
3 2 G=1 1 0
3 2 1 0 G=1
GAIN (dB)
GAIN (dB)
-1 -2 G=2 -3 -4 -5
05538-009
-1 -2 -3 -4 -5 -6 -7 1 10 FREQUENCY (MHz) 100
05538-012
VOUT = 0.2V p-p -6 -7 1 10 FREQUENCY (MHz) 100
VOUT = 2V p-p
G=2
Figure 11. Small Signal Frequency Response at Various Gains
80 70
Figure 14. Large Signal Frequency Response at Various Gains
0 -20 -40 MAGNITUDE 50 40 30 PHASE 20 10
05538-010
0.5 0.4 RL = 1k, VOUT = 2V p-p 0.3 0.2
GAIN (dB)
OPEN LOOP-GAIN (dB)
60
RL = 1k, VOUT = 0.2V p-p
-60 -80 -100 -120 -140 -160 -180 1000
0.1 0 -0.1 RL = 150, VOUT = 0.2V p-p -0.2 RL = 150, VOUT = 2V p-p -0.3 -0.4 -0.5 1 10 FREQUENCY (MHz)
0 -10 0.001
100
0.01
0.1
1
10
100
FREQUENCY (MHz)
Figure 12. 0.1 dB Flatness for Various Loads and Output Amplitudes
Figure 15. Open-Loop Gain and Phase Responses
Rev. 0 | Page 12 of 24
05538-016
OPEN LOOP-PHASE (Degrees)
AD8143
100 90 12V 100 VS = 12V
COMMON-MODE REJECTION (dB)
80 70 60 +5V 50 40 30 20
05538-020
5V
INPUT VOLTAGE NOISE (nV/Hz)
10 0 0.1 1 10 FREQUENCY (MHz) 100
1000
10 0.00001
0.0001
0.001
0.01
0.1
1
10
FREQUENCY (MHz)
Figure 16. Common-Mode Rejection Ratio vs. Frequency at Various Supplies
Figure 19. Input Referred Voltage Noise vs. Frequency
200 VOUT = 0.2V p-p 150
1.5 VOUT = 2V p-p 1.0
100
VOLTAGE (mV)
0.5
VOLTAGE (V)
50 0 -50 -100 G = 1, RL = 150 G = 1, RL = 1k G = 2, RL = 150 G = 2, RL = 1k
0
G = 1, RL = 150 G = 1, RL = 1k G = 2, RL = 150 G = 2, RL = 1k
-0.5
-1.0
05538-015 05538-018
-150 -200 0 10 20 30 40 50 TIME (ns) 60 70 80 90
-1.5 0 10 20 30 40 50 TIME (ns) 60 70 80 90
100
100
Figure 17. Small Signal Transient Response at Various Gains and Loads
Figure 20. Large Signal Transient Response at Various Gains and Loads
200 G = 2, CL = 2pF 150 G = 2, CL = 10pF, RSNUB = 40
1.5 G = 2, CL = 10pF, RSNUB = 40 G = 2, CL = 2pF 1.0
OUTPUT VOLTAGE (mV)
OUTPUT VOLTAGE (dB)
100 50 0 -50 -100 G = 1, CL = 2pF
05538-017
G = 1, CL = 2pF 0.5
0 RL = 1k VOUT = 2V p-p
-0.5
-200 0 10 20 30
G = 1, CL = 10pF, RSNUB = 40 40 50 TIME (ns) 60 70 80 90
-1.5 0 10 20 30 40 50 TIME (ns) 60 70 80 90
100
100
Figure 18. Small Signal Transient Response at Various Gains and 10 pF Capacitive Load Buffered by 40 Resistor
Figure 21. Large Signal Transient Response at Various Gains and 10 pF Capacitive Load Buffered by 40 Resistor
Rev. 0 | Page 13 of 24
05538-019
-150
RL = 1k VOUT = 0.2V p-p
-1.0
G = 1, C L = 10pF, RSNUB = 40
05538-021
AD8143
1.25 1.00 0.75 INPUT 0.50 0.5 0.4
1200 1400
0.3
SLEW RATE (V/s)
0.2
1000
VOLTAGE (V)
ERROR (%)
0.25 0 -0.25 -0.50 -0.75 OUTPUT -1.00 -1.25 0 10 20 30 40
ERROR
0.1 0 -0.1 -0.2 -0.3 -0.4
800 +SR, RL = 150 -SR, RL = 150 +SR, RL = 1k -SR, RL= 1k
600
400 200 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 OUTPUT VOLTAGE (V p-p)
50 TIME (ns)
60
70
80
90
-0.5 100
Figure 22. Settling Time (0.1%) at Various Loads
-50
05538-027
Figure 25. Slew Rate vs. Input Voltage Swing at Various Loads
-30
-55
-40
DISTORTION (dBc)
DISTORTION (dBc)
-60
-50
-60
-65
VS = 12V
-70
-70
VS = 5V
-80 Vs = 12V
-75
05538-047
Vs = 5V
-80 0.1
1
10 FREQUENCY (MHz)
100
-100 0.1
1
10 FREQUENCY (MHz)
100
Figure 23. Second Harmonic Distortion vs. Frequency and Power Supplies, VO = 2 V p-p, G = 2
-50
Figure 26. Third Harmonic Distortion vs. Frequency and Power Supplies, VO = 2 V p-p, G = 2
-30
-55
DISTORTION (dBc)
-40
DISTORTION (dBc)
-50
-60 VS = 12V -65 VS = 5V -70
05538-048
-60
-70
VS = 12V
-80
-75 0.1
1
10 FREQUENCY (MHz)
100
-90 0.1
1
10 FREQUENCY (MHz)
100
Figure 24. Second Harmonic Distortion vs. Frequency and Power Supplies, VO = 2 V p-p
Figure 27. Third Harmonic Distortion vs. Frequency and Power Supplies, VO = 2 V p-p
Rev. 0 | Page 14 of 24
05538-049
VS = 5V
05538-055
-90
05538-023
AD8143
54 52 50 48 46 44 IS- 42
05538-022
4 3
IS+
SUPPLY CURRENT (mA)
OUTPUT VOLTAGE (V)
VS = 12V RL =
2 1 0 -1 -2
05538-026
40 38 -5
-3 -4 -5
-4
-3
-2
-1
0
1
2
3
4
5
-4
-3
-2
-1
0
1
2
3
4
5
DIFFERENTIAL INPUT VOLTAGE (V)
DIFFERENTIAL INPUT VOLTAGE (V)
Figure 28. Power Supply Current vs. Differential Input Voltage at 12 V Supplies
60 55 50
SUPPLY CURRENT (mA)
Figure 31. Differential Input Operating Range
50
RL =
IS+, VS = 12V 45 IS-, VS = 12V
45 40 35 30 25 20
SUPPLY CURRENT (mA)
IS + 40 IS- 35
IS-, VS = 5V IS+, VS = 5V
30
05538-031
15 10 -50 -40 -30 -20 -10 0
RL = 25 5 6 7 8 9 10 11 12 SUPPLY VOLTAGE (VS)
10 20 30 40 50 60 70 80 90 100
TEMPERATURE (C)
Figure 29. Power Supply Current vs. Temperature
0 -10 -20 -30 VS = +5V VS = 5V
Figure 32. Power Supply Current vs. Power Supply Voltage
0 -10 -20 -30 VS = 5V VS = 12V
PSRR (dB)
-50 -60 -70 -80
VS = 12V
PSRR (dB)
-40
-40 -50 -60 -70 -80
05538-046
-90 -100 0.01 0.1 1 10 100
-90 -100 0.01
1000
0.1
1
10
100
1000
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure 30. Positive Power Supply Rejection Ratio vs. Frequency
Figure 33. Negative Power Supply Rejection Ratio vs. Frequency
Rev. 0 | Page 15 of 24
05538-045
05538-024
AD8143
15 G = +2 (RF = RG = 499) AND VS = 5V G = +5 (RF = 8.06k RG = 2k) AND VS = 12V +VSAT_12V
4.0 3.5 3.0 VS = 12V VS = 5V
10
OUTPUT VOLTAGE (V)
5
0
VOUT (V)
05538-025
+VSAT_5V
2.5 2.0 1.5
-5
-VSAT_5V
1.0
-10 -VSAT_12V -15 0 100 200 300 400 500 600 700 800 900 OUTPUT LOAD ()
05538-032
0.5 0 -25
1000
-20
-15
-10
-5
0 VIN (mV)
5
10
15
20
25
Figure 34. Output Saturation Voltage vs. Output Load
Figure 36. Comparator Hysteresis
6 5 4 3 2 2 x VIN G=2
VOLTAGE (V)
1 0 -1 -2 -3 -4 -5 -6 0 100 200 300 400 500 600 700 800 900 TIME (ns)
05538-029
OUTPUT
1000
Figure 35. Output Overdrive Recovery
Rev. 0 | Page 16 of 24
AD8143 THEORY OF OPERATION
The AD8143 amplifiers use an architecture called active feedback, which differs from that of conventional op amps. The most obvious differentiating feature is the presence of two separate pairs of differential inputs compared to a conventional op amp's single pair. Typically, for the active-feedback architecture, one of these input pairs is driven by a differential input signal, while the other is used for the feedback. This active stage in the feedback path is where the term active feedback is derived. The active feedback architecture offers several advantages over a conventional op amp in several types of applications. Among these are excellent common-mode rejection, wide input commonmode range, and a pair of inputs that are high impedance and completely balanced in a typical application. In addition, while an external feedback network establishes the gain response as in a conventional op amp, its separate path makes it entirely independent of the signal input. This eliminates any interaction between the feedback and input circuits, which traditionally causes problems with CMRR in conventional differential-input op amp circuits. Another advantage of active feedback is the ability to change the polarity of the gain merely by switching the differential inputs. A high input impedance inverting amplifier can therefore be made. Besides high input impedance, a unity-gain inverter with the AD8143 has noise gain of unity, producing lower output noise and higher bandwidth than op amps that have noise gain equal to 2 for a unity-gain inverter. The two differential input stages of the AD8143 are each transconductance stages that are well-matched. These stages convert the respective differential input voltages to internal currents. The currents are then summed and converted to a voltage, which is buffered to drive the output. The compensation capacitor is included in the summing circuit. When the feedback path is closed around the part, the output drives the feedback input to that voltage which causes the internal currents to sum to zero. This occurs when the two differential inputs are equal and opposite; that is, their algebraic sum is zero. In a closed-loop application, a conventional op amp has its differential input voltage driven to near zero under nontransient conditions. The AD8143 generally has differential input voltages at each of its input pairs, even under equilibrium conditions. As a practical consideration, it is necessary to internally limit the differential input voltage with a clamp circuit. Thus, the input dynamic ranges are limited to about 2.5 V for the AD8143 (see Specifications section for more detail). For this and other reasons, it is not recommended to reverse the input and feedback stages of the AD8143, even though some apparently normal functionality may be observed under some conditions.
Rev. 0 | Page 17 of 24
AD8143 APPLICATIONS
OVERVIEW
The AD8143 contains three independent active-feedback amplifiers that can be effectively applied as differential line receivers for red-green-blue (RGB) signals or component video, such as YPbPr, signals transmitted over unshielded-twisted-pair (UTP) cable. The AD8143 also contains two general-purpose comparators with hysteresis that can be used to receive digital signals or to extract video synchronization pulses from received common-mode signals that contain encoded synchronization signals. An internal linear voltage regulator derives power for the comparators from the positive supply; therefore, the AD8143 must always have a minimum positive supply voltage of 4.5 V. The AD8143 includes a power-down feature that can be asserted to reduce the supply current when a particular device is not in use. In this configuration, the voltage applied to the REF pin appears at the output with a gain of 1 + RF/RG. To achieve unity gain from VREF to VOUT in this configuration, divide VREF by the same factor used in the feedback loop; the same RF and RG values can be used. Figure 38 illustrates this approach.
+5V 0.01F + VIN RF VREF RG RG - + REF - FB RF VOUT
0.01F -5V
05538-039
BASIC CLOSED-LOOP GAIN CONFIGURATIONS
As described in the Theory of Operation section, placing a resistive feedback network between an amplifier output and its respective feedback amplifier input creates a stable negative feedback amplifier. It is important to note that the closed-loop gain of the amplifier used in the signal path is defined as the amplifier's single-ended output voltage divided by its differential input voltage. Therefore, each amplifier in the AD8143 provides differential-to-single-ended gain. Additionally, the amplifier used for feedback has two high impedance inputs--the FB input, where the negative feedback is applied, and the REF input, which can be used as an independent single-ended input to apply a dc offset to the output signal. Some basic gain configurations implemented with an AD8143 amplifier are shown in Figure 37 through Figure 39.
+5V 0.01F + VIN - + REF - FB VREF RG RF VOUT
Figure 38. Basic Gain Circuit: VOUT = VIN (1 + RF/RG) + VREF
The gain equation for the circuit in Figure 38 is VOUT = VIN (1 + RF/RG) + VREF (2)
Another configuration that provides the same gain equation as Equation 2 is shown in Figure 39. In this configuration, it is important to keep the source resistance of VREF much smaller than RG to avoid gain errors.
+5V 0.01F + VIN - REF FB RG VREF -5V RF + - VOUT
0.01F
05538-040
Figure 39. Basic Gain Circuit: VOUT = VIN (1 + RF/RG) + VREF
0.01F -5V
05538-038
Figure 37. Basic Gain Circuit: VOUT = (VIN + VREF)(1 + RF/RG)
The gain equation for the circuit in Figure 37 is VOUT = (VIN + VREF)(1 + RF/RG) (1)
For stability reasons, the inductance of the trace connected to the REF pin must be kept to less than 10 nH. The typical inductance of 50 traces on the outer layers of the FR-4 boards is 7 nH/in, and on the inner layers, it is typically 9 nH/in. Vias must be accounted for as well. The inductance of a typical via in a 0.062-inch board is on the order of 1.5 nH. If longer traces are required, a 200 resistor should be placed in series with the trace to reduce the Q-factor of the inductance.
Rev. 0 | Page 18 of 24
AD8143
In many dual-supply applications, VREF can be directly connected to ground right at the device.
INPUT CLAMPING
The differential input that is assigned to receive the input signal includes clamping diodes that limit the differential input swing to approximately 5.5 V p-p at 25C. Because of this, the input and feedback stages should never be interchanged. Figure 31 illustrates the clamping action at the signal input stage. The supply current drawn by the AD8143 has a strong dependence on input signal magnitude because the input transconductance stages operate with differential input signals that can be up to a few volts peak-to-peak. This behavior is distinctly different from that of traditional op-amps, where the differential input signal is driven to essentially 0 V by negative feedback. Figure 28 illustrates the supply current dependence on input voltage. For most applications, including receiving RGB video signals, the input signal magnitudes encountered are well within the safe operating limits of the AD8143 over its full power supply and operating temperature ranges. In some extreme applications where large differential and/or common-mode voltages can be encountered, external clamping may be necessary. Another application where external common-mode clamping is sometimes required is when an unpowered AD8143 receives a signal from an active driver. In this case, external diodes are required when the current drawn by the internal ESD diodes cannot be kept to less than 5 mA. When using 12 V supplies, the differential input signal must be kept to less than 4 V p-p. In applications that use 12 V supplies where the input signals are expected to reach or exceed 4 V p-p, external differential clamping at a maximum of 4 V p-p is required. Figure 42 shows a general approach to external differentialmode clamping.
POSITIVE CLAMP RS + NEGATIVE CLAMP
TERMINATING THE INPUT
One of the key benefits of the active-feedback architecture is the separation that exists between the differential input signal and the feedback network. Because of this separation, the differential input maintains its high CMRR and provides high differential and common-mode input impedances, making line termination a simple task. Most applications that use the AD8143 involve transmitting broadband video signals over 100 UTP cable and use dc-coupled terminations. The two most common types of dc-coupled terminations are differential and common-mode. Differential termination of 100 UTP is implemented by simply connecting a 100 resistor across the amplifier input, as shown in Figure 40.
+5V 0.01F 100 UTP 100 + VIN - + REF - FB RG RF VOUT
0.01F -5V
05538-041
Figure 40. Differential-Mode Termination
Some applications require common-mode terminations for common-mode currents generated at the transmitter. In these cases, the 100 termination resistor is split into two 50 resistors. The required common-mode termination voltage is applied at the tap between the two resistors. In many of these applications, the common-mode tap is connected to ground (VTERM (CM) = 0). This scheme is illustrated in Figure 41.
+5V 0.01F + VIN - + REF - FB VTERM(CM) RG RF VOUT
VIN
RT RS + VOUT -
50 100 UTP 50
-
Figure 42. Differential-Mode Clamping
-5V
Figure 41. Common-Mode Termination
05538-042
0.01F
The positive and negative clamps are nonlinear devices that exhibit very low impedance when the voltage across them reaches a critical threshold (clamping voltage), thereby limiting the voltage across the AD8143 input. The positive clamp has a positive threshold, and the negative clamp has a negative threshold.
Rev. 0 | Page 19 of 24
05538-051
AD8143
A diode is a simple example of such a clamp. Schottky diodes generally have lower clamping voltages than typical signal diodes. The clamping voltage should be larger than the largest expected signal amplitude, with enough margin to ensure that the received signal passes without being distorted. A simple way to implement a clamp is to use a number of diodes in series. The resultant clamping voltage is then the sum of the clamping voltages of individual diodes. A 1N4448 diode has a forward voltage of approximately 0.70 V to 0.75 V at typical current levels that are seen when it is being used as a clamp, and 2 pF maximum capacitance at 0 V bias. (The capacitance of a diode decreases as its reverse bias voltage is increased.) The series connection of two 1N4448 diodes, therefore, has a clamping voltage of 1.4 V to 1.5 V. Figure 43 shows how to limit the differential input voltage applied to an AD8143 amplifier to 1.4 V to 1.5 V (2.8 V p-p to 3.0 V p-p). Note that the resulting capacitance of the two series diodes is half that of one diode. Different numbers of series diodes can be used to obtain different clamping voltages. RT is the differential termination resistor and the series resistances, RS, limit the current into the diodes. The series resistors should be highly matched in value to preserve high frequency CMRR.
POSITIVE CLAMP + RS NEGATIVE CLAMP
V+ 2 RS
+
3
VIN
HBAT-540C 1 V- RT V+ 2 RS 3
+ - VOUT
-
HBAT-540C
1 V-
Figure 44. External Common-Mode Clamping
The series resistances, RS, limit the current in each leg, and the Schottky diodes limit the voltages on each input to approximately 0.3 V to 0.4 V over the positive power supply, V+ and to 0.3 V to 0.4 V below the negative power supply, V-. The maximum value of RS is determined by the required signal bandwidth, the line impedance, and the effective differential capacitance due to the AD8143 inputs and the diodes. As with the differential clamp, the series resistors should be highly matched in value to preserve high frequency CMRR.
PRINTED CIRCUIT BOARD LAYOUT CONSIDERATIONS
The two most important issues with regard to printed circuit board (PCB) layout are minimizing parasitic signal trace reactances in the feedback network and providing sufficient thermal relief. Excessive parasitic reactances in the feedback network cause excessive peaking in the amplifier's frequency response and excessive overshoot in its step response due to a reduction in phase margin. Oscillation occurs when these parasitic reactances are increased to a critical point where the phase margin is reduced to zero. Minimizing these reactances is important to obtain optimal performance from the AD8143. When operating at 12 V power, it is important to pay special attention to removing heat from the AD8143. Besides the special layout considerations previously mentioned and expounded upon in the following sections, general high speed layout practices must be adhered to when applying the AD8143. Controlled impedance transmission lines are required for incoming and outgoing signals, referenced to a ground plane.
05538-052
VIN
RT RS + VOUT -
-
Figure 43. Using Two 1N4448 Diodes in Series as a Clamp
There are many other nonlinear devices that can be used as clamps. The best choice for a particular application depends upon the desired clamping voltage, response time, parasitic capacitance, and other factors. When using external differential-mode clamping, it is important to ensure that the series resistors (RS), the sum of the parasitic capacitance of the clamping devices, and the input capacitance of the AD8143 are small enough to preserve the desired signal bandwidth. Figure 44 shows a specific example of external common-mode clamping.
Rev. 0 | Page 20 of 24
05538-044
AD8143
Typically, the input signals are received over 100 differential transmission lines. A 100 differential transmission line is readily realized on the printed circuit board using two wellmatched, closely-spaced 50 single-ended traces that are coupled through the ground plane. The traces that carry the single-ended output signals are most often 75 for video signals. Output signal connections should include series termination resistors that are matched to the impedance of the line they are driving. Broadband power supply decoupling networks should be placed as close as possible to the supply pins. Small surface-mount ceramic capacitors are recommended for these networks, and tantalum capacitors are recommended for bulk supply decoupling. A conservative estimate for feedback-loop trace capacitance in each loop of the layout shown in Figure 45 is 2 pF. This value is viewed as the minimum load capacitance and is reflected in the frequency response and transient response plots.
Maximizing Heat Removal
The AD8143 pinout includes ground connections on its corner pins to facilitate heat removal. These pins should be connected to the exposed paddle on the underside of the AD8143 and to a ground plane on the component side of the board. Additionally, a 5 x 5 array of thermal vias connecting the exposed paddle to internal ground planes should be placed inside the PCB pad that is soldered to the exposed paddle. Using these techniques is highly recommended in all applications, and is required in 12 V applications where power dissipation is the greatest. Figure 45 illustrates how to optimize the circuit board layout for heat removal. Designs must often conform to design-for-manufacturing (DFM) rules that stipulate how to lay out PCBs in such a way as to facilitate the manufacturing process. Some of these rules require thermal relief on pads that connect to planes, and the rules may preclude the use of the technique illustrated in Figure 45. In these cases, the ground pins should be connected to the exposed paddle and component-side ground plane using techniques that conform to the DFM requirements.
GND
Minimizing Parasitic Reactances in the Feedback Network
Parasitic trace capacitance and inductance are both reduced when the traces that connect the feedback network together are reduced in length. Removing the copper from all planes below the traces reduces trace capacitance, but increases trace inductance because the loop area formed by the trace and ground plane is increased. A reasonable compromise that works well is to void all copper directly under the feedback loop traces and component pads with margins on each side approximately equal to one trace width. Combining this technique with minimizing trace lengths is effective in keeping parasitic trace reactances in the feedback loop to a minimum. Additionally, all components used in the feedback network should be in 0402 surface-mount packages. Figure 45 illustrates the magnified view of a proven feedback network layout that provides excellent performance. Note that the internal layers are not shown. It is strongly recommended that the layout shown in Figure 45, or something very similar, be used for the three AD8143 feedback networks.
GND RGG
CFG
RGB CFB RFB GND
RFG
GND
= COMPONENT SIDE = CIRCUIT SIDE GND RFR RGR GND CFR
05538-043
GND
Figure 45. Recommended Layout for Feedback Loops and Grounding
Rev. 0 | Page 21 of 24
AD8143
DRIVING A CAPACITIVE LOAD
The AD8143 typically drives either high impedance loads, such as crosspoint switch inputs, or doubly terminated coaxial cables. A gain of 1 is commonly used in the high impedance case because the 6 dB transmission line termination loss is not incurred. A gain of 2 is required when driving cables to compensate for the 6 dB termination loss. In all cases, the output must drive the parasitic capacitance of the feedback loop, conservatively estimated to be 2 pF, in addition to the capacitance presented by the actual load. When driving a high impedance input, it is recommended that a small series resistor be used to buffer the input capacitance of the device being driven. Clearly, the resistor value must be small enough to preserve the required bandwidth. In the ideal doubly terminated cable case, the AD8143 output sees a purely resistive load. In reality, there is some residual capacitance, and this is buffered by the series termination resistor. Figure 46 illustrates the high impedance case, and Figure 47 illustrates the cabledriving case.
+5V
Small and large signal frequency responses for the High-Z case with a 40 series resistor and 10 pF load capacitance are shown in Figure 10 and Figure 13; transient responses for the same conditions are shown in Figure 18 and Figure 21. In the cable driving case shown in Figure 47, CS << 2 pF for a well-designed circuit; therefore, the feedback loop capacitance is the dominant capacitive load. The feedback loop capacitance is present for all cases, and its effect is included in the data presented in the Typical Performance Characteristics and Specifications tables.
POWER-DOWN
The power-down feature is intended to be used to reduce power consumption when a particular device is not in use, and does not place the output in a High-Z state when asserted. The power-down feature is asserted when the voltage applied to the power-down pin drops to approximately 2 V below the positive supply. The AD8143 is enabled by pulling the power-down pin to the positive supply.
COMPARATORS
In addition to general-purpose applications, the two on-chip comparators can be used to receive differential digital information or to decode video sync pulses from received common-mode voltages. Built-in hysteresis helps to eliminate false triggers from noise. The comparator outputs are not designed to drive transmission lines. When the signals detected by the comparators are driven over cables or controlled impedance printed circuit board traces, the comparator outputs must be fed to a spare logic gate, FPGA, or other device that is capable of driving signals over transmission lines. An internal linear voltage regulator derives power for the comparators from the positive supply; therefore, the AD8143 must always have a minimum positive supply voltage of 4.5 V.
0.01F + VIN - REF CIN FB RG RF RS
-5V
05538-053
0.01F
Figure 46. Buffering the Input Capacitance of a High-Z Load
+5V
SYNC PULSE EXTRACTION USING COMPARATORS
The AD8143 is particularly useful in keyboard video mouse (KVM) applications. KVM networks transmit and receive computer video signals, which are typically comprised of red, green, and blue (RGB) video signals and separate horizontal and vertical sync signals. Because the sync signals are separate and not embedded in the color signals, it is advantageous to transmit them using a simple scheme that encodes them among the three common-mode voltages of the RGB signals. The AD8134 triple differential driver is a natural complement to the AD8143 and performs the sync pulse encoding with the necessary circuitry on-chip.
0.01F + VIN - REF CS FB RG RF RL RS
-5V
Figure 47. Driving a Doubly Terminated Cable
Rev. 0 | Page 22 of 24
05538-054
0.01F
AD8143
The AD8134 encoding equations are given in Equation 3, Equation 4, and Equation 5.
where: Red VCM, Green VCM, and Blue VCM are the transmitted commonmode voltages of the respective color signals. K is a an adjustable gain constant that is set by the AD8134. (4) (5) V and H are the vertical and horizontal sync pulses, defined with a weight of -1 when the pulses are in their low states, and a weight of +1 when they are in their high states. The AD8134 data sheet contains further details regarding the encoding scheme. Figure 48 illustrates how the AD8143 comparators can be used to extract the horizontal and vertical sync pulses that are encoded on the RGB common-mode voltages by the AD8134.
Red VCM
K = V -H 2
[
]
(3)
Green VCM = Blue VCM
K -2 V 2
[
]
K = V +H 2
[
]
50 RECEIVED RED VIDEO RED CMV HSYNC 50
1k
50 RECEIVED GREEN VIDEO GREEN CMV VSYNC 50
1k
50 RECEIVED BLUE VIDEO BLUE CMV
05538-057
50
Figure 48. Extracting Sync Signals from Received Common-Mode Signals
Rev. 0 | Page 23 of 24
AD8143 OUTLINE DIMENSIONS
5.00 BSC SQ 0.60 MAX 0.60 MAX
25 24 32 1
PIN 1 INDICATOR
PIN 1 INDICATOR TOP VIEW 4.75 BSC SQ
0.50 BSC
EXPOSED PAD (BOTTOM VIEW)
3.45 3.30 SQ 3.15
8
0.50 0.40 0.30 0.80 MAX 0.65 TYP 0.05 MAX 0.02 NOM SEATING PLANE 0.30 0.23 0.18 0.20 REF
17 16
9
0.25 MIN 3.50 REF
12 MAX
1.00 0.85 0.80
COPLANARITY 0.08
COMPLIANT TO JEDEC STANDARDS MO-220-VHHD-2
Figure 49. 32-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 5 mm x 5 mm Body, Very Thin Quad (CP-32-3) Dimensions shown in millimeters
ORDERING GUIDE
Model AD8143ACPZ-R2 1 AD8143ACPZ-REEL1 AD8143ACPZ-REEL71
1
Temperature Range -40C to +85C -40C to +85C -40C to +85C
Package Description 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 32-Lead Lead Frame Chip Scale Package (LFCSP_VQ)
Package Option CP-32-3 CP-32-3 CP-32-3
Z = Pb-free part.
(c) 2005 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D05538-0-10/05(0)
Rev. 0 | Page 24 of 24

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